The likelihood of mixing differential ECL (Emitter-Coupled Logic) logic signals with TTL (Transistor-Transistor Logic)/CMOS (Complementary Metal Oxide Semiconductor) logic signals in a single application is increasing especially as microprocessor based system frequencies and complexity increase. In particular, the use of differential ECL signals is needed in order to maintain signal integrity and reduce noise at high frequencies. Moreover, in synchronous systems, these differential ECL signals must be in phase with the TTL/CMOS signals.
The basic problem in mixing differential ECL signals and TTL/CMOS signals is that the differential ECL signal path is substantially different from a single ended TTL/CMOS signal path. Moreover, these signal paths differ with process and system variations.
Referring to FIG. 1, there is illustrated a detailed block diagram of a traditional prior art approach to this problem. Differential ECL input signal is supplied to differential ECL signal path block 12 as well as ECL to TTL/CMOS translation block 14 wherein it is understood that block 14 may be either an ECL-TTL translator or an ECL-CMOS translator. The output of ECL signal path block 12 is passed through delay component 16 to provide a differential ECL output signal. Also, the output of translation block 14 provides a TTL/CMOS output signal.
The basic problem is that the signal path having the ECL-TTL/CMOS translation block is much slower than the straight ECL signal path. For example, a typical state of the art ECL-TTL translator may have a propagation delay of 3 ns (nanoseconds). Moreover, a state of the art ECL-CMOS translator may have a propagation delay of 2.5 ns. Thus, delay component 16 must be used to match the ECL signal path with the TTL/CMOS signal path. However, due to the long delays of the translation blocks, maintaining good delay matching while considering process, temperature and voltage supply variation is cumbersome if not impossible for systems operating at high frequencies.
Hence, there exists a need for an improved technique for providing phase synchronization of ECL logic signals and TTL/CMOS logic signals.